Etch features with reduced line edge roughness

ABSTRACT

A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less than 100 nm is formed over the sidewalls of the photoresist features by performing for a plurality of cycles. Each cycle comprises depositing a layer on the photoresist layer wherein the deposited layer has a thickness between a monolayer to 20 nm. Features are etched into the layer through the photoresist features. The photoresist layer and sidewall layer are stripped.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of prior U.S. patent application Ser.No. 11/208,098 (Atty. Dkt. No. LAM1P212/P1424), entitled “Etch Featureswith Reduced Line Edge Roughness”, filed on Aug. 18, 2005, by inventorsSadjadi et al., which is incorporated herein by reference and from whichpriority under 35 U.S.C. § 120 is claimed.

BACKGROUND OF THE INVENTION

The present invention relates to the formation of semiconductor devices.

During semiconductor wafer processing, features of the semiconductordevice are defined in the wafer using well-known patterning and etchingprocesses. In these processes, a photoresist (PR) material is depositedon the wafer and then is exposed to light filtered by a reticle. Thereticle is generally a glass plate that is patterned with exemplaryfeature geometries that block light from propagating through thereticle.

After passing through the reticle, the light contacts the surface of thephotoresist material. The light changes the chemical composition of thephotoresist material such that a developer can remove a portion of thephotoresist material. In the case of positive photoresist materials, theexposed regions are removed, and in the case of negative photoresistmaterials, the unexposed regions are removed. Thereafter, the wafer isetched to remove the underlying material from the areas that are nolonger protected by the photoresist material, and thereby define thedesired features in the wafer.

One problem in such processes is that microscopic photoresist structureswith small widths are likely to change shape during processing. Thisdeformation may be transferred into the film being etched, yielding etchstructures, which deviate from the intended shape, dimension, orroughness. These etch-induced photoresist transformations may beclassified in groups such as line edge roughening, surface roughening,and line wiggling. Line edge roughness (LER) refers to the edges ofpatterned lines becoming more irregular as the pattern is transferredfrom photoresist to the underlying film.

SUMMARY OF THE INVENTION

To achieve the foregoing and in accordance with the purpose of thepresent invention a method for forming a feature in a layer with reducedline edge roughening is provided. A photoresist layer is formed over thelayer. The photoresist layer is patterned to form photoresist featureswith photoresist sidewalls. A sidewall layer with a thickness less than100 nm is formed over the sidewalls of the photoresist features byperforming for a plurality of cycles. Each cycle comprises depositing alayer on the photoresist layer wherein the deposited layer has athickness between a monolayer to 20 nm. Features are etched into thelayer through the photoresist features. The photoresist layer andsidewall layer are stripped.

In another manifestation of the invention a method for forming a featurein an etch layer with reduced line edge roughening is provided. Apatterned photoresist layer is formed over the etch layer to formphotoresist features with photoresist sidewalls. A sidewall layer with athickness less than 100 nm is formed over the sidewalls of thephotoresist features, comprising performing for a plurality of cycles.Each cycle comprises depositing a layer on the photoresist layer whereinthe deposited layer has a thickness between a monolayer to 20 nm andetching back the deposited layer to remove parts of the deposited layerformed over bottoms of the photoresist features, while leaving asidewall layer. Features are etched into the etch layer through thephotoresist features. The photoresist layer and sidewall layer arestripped, where the depositing the layer on the photoresist layer, theetching back, the etching features, and stripping are done in situ in asingle plasma chamber.

These and other features of the present invention will be described inmore detail below in the detailed description of the invention and inconjunction with the following figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings and in whichlike reference numerals refer to similar elements and in which:

FIG. 1 is a high level flow chart of a process that may be used in anembodiment of the invention.

FIGS. 2A-D are schematic cross-sectional views of a stack processedaccording to an embodiment of the invention.

FIG. 3 is a more detailed flow chart of the step of depositing a layerover sidewalls of photoresist features to reduce CD.

FIG. 4 is a schematic view of a plasma processing chamber that may beused in practicing the invention.

FIGS. 5A-B illustrate a computer system, which is suitable forimplementing a controller used in embodiments of the present invention.

FIGS. 6A-B are schematic cross-sectional views of a stack processedaccording to an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described in detail with reference toa few preferred embodiments thereof as illustrated in the accompanyingdrawings. In the following description, numerous specific details areset forth in order to provide a thorough understanding of the presentinvention. It will be apparent, however, to one skilled in the art, thatthe present invention may be practiced without some or all of thesespecific details. In other instances, well known process steps and/orstructures have not been described in detail in order to notunnecessarily obscure the present invention.

Line edge roughening is believed to be caused by non-uniform deposition,ion sputtering by ions coming at a steep angle relative to the lines,lack of mobility of the photoresist or mask, stress mismatch between thephotoresist, mask and etch by products (polymers), and photoresist ormask chemical modifications. Although line edge roughening manifestsitself in different forms, the same factors can also cause twisting orwiggling of the photoresist or mask. Rather than just a roughening ofthe photoresist, wiggling or twisting refers to a change in the shape ofthe line as viewed from above, with a length scale similarly to thewidth of the line. Wiggling specifically refers to the modification ofnarrow line structures, which result from the roughening of thephotoresist. Line edge roughening may be seen for dense contact or densecell etch, where the faceting of the photoresist may lead to formationof very thin structures at the top of the photoresist. Despite differentformulations of resist and masks used for different lithographytechnologies, wiggling has been observed for deep ultraviolet DUVphotoresist, 193 nm photoresist, and even harder masks such as amorphouscarbon.

The detailed mechanism, which causes wiggling, is not well-understood,but can be attributed to factors previously mentioned. However, it hasbeen shown that excessive polymer deposition on top of the photoresistlines can induce wiggling. This is believed to be caused by stress inthe deposited film, which tends to pull the photoresist out of shape.The problem may be aggravated by the tendency of photoresist, especially193 nm varieties, to soften during etch processing. This mechanism doesnot explain all instances of wiggling. In some cases, a process isclearly etching the photoresist, no depositing, yet the photoresist maywiggle. Wiggling may be related to modification of the photoresistcomposition during the etch, which is more severe for 193 nmphotoresist.

To facilitate understanding, FIG. 1 is a high level flow chart of aprocess that may be used in an embodiment of the invention. A patternedphotoresist mask is provided (step 104). FIG. 2A is a schematiccross-sectional view of a layer to be etched 208 over a substrate 204,with a patterned photoresist mask 212 with a feature 214, over a ARL210, over the etch layer 208 forming a stack 200. The photoresist maskhas a photoresist feature critical dimension (CD), which may be thewidest part of the width 316 of the smallest possible feature.Presently, for 248 nm photoresist a typical CD for the photoresist maybe 230-250 nm, using conventional processes. To provide the patternedphotoresist mask, a photoresist layer may be first formed over the layerto be etched. Then the photoresist layer is patterned to formphotoresist features with photoresist sidewalls.

A sidewall layer is formed over the sidewalls of the photoresistfeatures (step 108). FIG. 2B is a schematic cross-sectional view of thepatterned photoresist mask 212 with a sidewall layer 220 formed over thesidewalls of the feature 214. The sidewall layer preferably formssubstantially vertical and conformal sidewalls. An example of asubstantially vertical sidewall is a sidewall that from bottom to topmakes an angle of between 88° to 90° with the bottom of the feature.Conformal sidewalls have a deposition layer that has substantially thesame thickness from the top to the bottom of the feature. Non-conformalsidewalls may form a faceting or a bread-loafing formation, whichprovide non-substantially vertical sidewalls. Tapered sidewalls (fromthe faceting formation) or bread-loafing sidewalls may increase thedeposited layer CD and provide a poor etching mask.

A break through etch may be used to etch through any remaining depositedlayer immediately above the etch layer any other intermediate layerabove the etch layer (step 112).

Features are then etched into the layer to be etched 208 through theformed sidewall layer 220 (step 116). FIG. 2C shows a feature 232 etchedinto the layer to be etched 208.

The photoresist and sidewall layer may then be stripped (step 120). Thismay be done as a single step or two separate steps with a separatedeposited layer removal step and photoresist strip step. Ashing may beused for the stripping process. FIG. 2D shows the stack 200 after thedeposited layer and photoresist mask have been removed. Additionalformation steps may be performed (step 124). For example, a contact 240may then be formed in the feature. To provide a dual damascenestructure, a trench may be etched before the contact is formed.Additional processes may be performed after the contact is formed.

FIG. 3 is a more detailed flow chart of an embodiment of the forming asidewall layer over sidewalls of the photoresist features (step 108).This step is a cyclical step that is repeated at least twice. Aconformal layer is deposited over the photoresist layer (step 304). Theconformal layer is then etched back to remove any deposition at thebottom of the photoresist features to form the sidewall layers (step308).

EXAMPLE

In one example, a substrate 204, with the layer to be etched 208, an ARClayer 210, and a patterned photoresist mask 212 is placed in an etchchamber.

FIG. 4 is a schematic view of an processing chamber 400 that may be usedfor forming the sidewall layer, etching, and stripping. The plasmaprocessing chamber 400 comprises confinement rings 402, an upperelectrode 404, a lower electrode 408, a gas source 410, and an exhaustpump 420. The gas source 410 comprises a deposition gas source 412 andan etch back gas source 416. The gas source 410 may comprise additionalgas sources, such as an etching gas source 418. Within plasma processingchamber 400, the substrate 204 is positioned upon the lower electrode408. The lower electrode 408 incorporates a suitable substrate chuckingmechanism (e.g., electrostatic, mechanical clamping, or the like) forholding the substrate 204. The reactor top 428 incorporates the upperelectrode 404 disposed immediately opposite the lower electrode 408. Theupper electrode 404, lower electrode 408, and confinement rings 402define the confined plasma volume. Gas is supplied to the confinedplasma volume by the gas source 410 and is exhausted from the confinedplasma volume through the confinement rings 402 and an exhaust port bythe exhaust pump 420. A first RF source 444 is electrically connected tothe upper electrode 404. A second RF source 448 is electricallyconnected to the lower electrode 408. Chamber walls 452 surround theconfinement rings 402, the upper electrode 404, and the lower electrode408. Both the first RF source 444 and the second RF source 448 maycomprise a 27 MHz power source and a 2 MHz power source. Differentcombinations of connecting RF power to the electrode are possible. Inthe case of Lam Research Corporation's Dual Frequency Capacitive (DFC)System, made by LAM Research Corporation™ of Fremont, Calif., which maybe used in a preferred embodiment of the invention, both the 27 MHz and2 MHz power sources make up the second RF power source 448 connected tothe lower electrode, and the upper electrode is grounded. A controller435 is controllably connected to the RF sources 444, 448, exhaust pump420, and the gas source 410. The DFC System would be used when the layerto be etched 208 is a dielectric layer, such as silicon oxide or organosilicate glass.

FIGS. 5A and 5B illustrate a computer system 1300, which is suitable forimplementing a controller 435 used in embodiments of the presentinvention. FIG. 5A shows one possible physical form of the computersystem. Of course, the computer system may have many physical formsranging from an integrated circuit, a printed circuit board, and a smallhandheld device up to a huge super computer. Computer system 1300includes a monitor 1302, a display 1304, a housing 1306, a disk drive1308, a keyboard 1310, and a mouse 1312. Disk 1314 is acomputer-readable medium used to transfer data to and from computersystem 1300.

FIG. 5B is an example of a block diagram for computer system 1300.Attached to system bus 1320 is a wide variety of subsystems.Processor(s) 1322 (also referred to as central processing units, orCPUs) are coupled to storage devices, including memory 1324. Memory 1324includes random access memory (RAM) and read-only memory (ROM). As iswell known in the art, ROM acts to transfer data and instructionsuni-directionally to the CPU and RAM is used typically to transfer dataand instructions in a bi-directional manner. Both of these types ofmemories may include any suitable of the computer-readable mediadescribed below. A fixed disk 1326 is also coupled bi-directionally toCPU 1322; it provides additional data storage capacity and may alsoinclude any of the computer-readable media described below. Fixed disk1326 may be used to store programs, data, and the like and is typicallya secondary storage medium (such as a hard disk) that is slower thanprimary storage. It will be appreciated that the information retainedwithin fixed disk 1326 may, in appropriate cases, be incorporated instandard fashion as virtual memory in memory 1324. Removable disk 1314may take the form of any of the computer-readable media described below.

CPU 1322 is also coupled to a variety of input/output devices, such asdisplay 1304, keyboard 1310, mouse 1312, and speakers 1330. In general,an input/output device may be any of: video displays, track balls, mice,keyboards, microphones, touch-sensitive displays, transducer cardreaders, magnetic or paper tape readers, tablets, styluses, voice orhandwriting recognizers, biometrics readers, or other computers. CPU1322 optionally may be coupled to another computer or telecommunicationsnetwork using network interface 1340. With such a network interface, itis contemplated that the CPU might receive information from the network,or might output information to the network in the course of performingthe above-described method steps. Furthermore, method embodiments of thepresent invention may execute solely upon CPU 1322 or may execute over anetwork such as the Internet in conjunction with a remote CPU thatshares a portion of the processing.

In addition, embodiments of the present invention further relate tocomputer storage products with a computer-readable medium that havecomputer code thereon for performing various computer-implementedoperations. The media and computer code may be those specially designedand constructed for the purposes of the present invention, or they maybe of the kind well known and available to those having skill in thecomputer software arts. Examples of computer-readable media include, butare not limited to: magnetic media such as hard disks, floppy disks, andmagnetic tape; optical media such as CD-ROMs and holographic devices;magneto-optical media such as floptical disks; and hardware devices thatare specially configured to store and execute program code, such asapplication-specific integrated circuits (ASICs), programmable logicdevices (PLDs) and ROM and RAM devices. Examples of computer codeinclude machine code, such as produced by a compiler, and filescontaining higher level code that are executed by a computer using aninterpreter. Computer readable media may also be computer codetransmitted by a computer data signal embodied in a carrier wave andrepresenting a sequence of instructions that are executable by aprocessor.

In the etch chamber, a sidewall layer is formed over the sidewalls ofthe photoresist features (step 108). An example recipe for thedeposition of the conformal layer (step 304), the deposition gas source412 provides a flow of 150 sccm CH₃F, 75 sccm N₂, and 100 sccm Ar. Thepressure is set to 80 mTorr. The substrate is maintained at atemperature of 20° C. The second RF source 448 provides 400 Watts at afrequency of 27 MHz and 0 Watts a frequency of 2 MHz.

FIG. 6A is a schematic cross-sectional view of a substrate 604 under anetch layer 608, under an ARC layer 610, under a patterned photoresistlayer 612, under a deposited conformal layer 620. In this example, theconformal layer 620 covers the sidewalls and top of the photoresistlayer 612 and the ARC 610 at the bottom of the photoresist features 614.In other embodiments, the conformal layer might not be deposited on theARC at the bottom of the photoresist features. Preferably, the depositedconformal layer is between a monolayer to 20 nm thick. More preferably,the deposited conformal layer is between a monolayer and 7 nm thick.Most preferably, the deposited conformal layer is between a monolayerand 2 nm thick.

Preferably, the depositing the conformal layer comprises at least one ofatomic layer deposition, chemical vapor deposition, sputteringdeposition, plasma deposition, and plasma enhanced chemical vapordeposition. More preferably, the depositing the conformal layercomprises at least one of chemical vapor deposition. sputteringdeposition, plasma deposition, and enhanced chemical vapor deposition.Preferably, the substrate temperature is maintained between −80° C. and120° C. Generally, 120° C. is the glass transition temperature ofphotoresist. It is preferred to keep the substrate temperature belowthat glass transition temperature of the photoresist. More preferably,the substrate temperature is maintained between −10° C. and 50° C. Mostpreferably, the substrate temperature is maintained at 20° C.Preferably, the bias potential is less than 120 volts. More preferably,the bias potential is less that 100 volts. Most preferably, the biaspotential is between 20 and 80 volts.

Preferably, the deposited layer comprises at least one of polymer, TEOS,SiO₂, Si₃N₂, SiC, Si, Al₂O₃, AlN, Cu, HfO₂, Mo, Ta, TaN, TaO₂, Ti, TiN,TiO₂, TiSiN, and W. A polymer is a hydrocarbon based material, such as afluorohydrocarbon material.

During the etch back (step 308), a halogen (i.e. fluorine, bromine,chlorine) containing gas, such as 100 sccm CF₄, is provided. In thisexample, CF₄ is the only gas provided during the etch back. A pressureof 20 mTorr is provided to the chamber. The second RF source 448provides 600 Watts at a frequency of 27 MHz and 0 Watts a frequency of 2MHz.

FIG. 6B is a schematic cross-sectional view of a substrate 604 under anetch layer 608, under an ARC layer 610, under a patterned photoresistlayer 612 after the conformal layer has been etched back to formsidewalls 624 from the deposited conformal layer. In this example, theparts of the conformal layer covering the top of the photoresist layer612 and the ARC at the bottom of the photoresist features 614 isremoved, leaving only a layer on the sidewalls of the photoresistfeatures. In other embodiments, the part of the conformal layer over thetop of the photoresist may remain, so that only the layer at the bottomof the photoresist features over the ARC is removed by the etch back.However, in such an embodiment, some of the conformal layer over the topof the photoresist is removed. In such an embodiment, the conformallayer remaining over the top of the photoresist layer may be used as anetch hard mask.

In this example, the cycle of forming the sidewalls (step 108)comprising the steps of depositing the conforming layer (step 304) andetching back (step 308) is performed using at least 2 cycles. Morepreferably, the forming the sidewalls is performed between 3 and 50cycles. Most preferably, the forming the sidewalls is performed between3 and 10 cycles. Preferable the completed sidewall layers are thin andetch resistant, such as less than 100 nm thick. More preferably, thecompleted sidewall layers are between a monolayer and 50 nm thick. Mostpreferably, the complete sidewall layers are between a monolayer and 2nm thick.

In other embodiments etch cycle may further include additionaldeposition and/or etch back steps.

An example of a break through etch recipe may be used to remove anyremaining deposited layer on the bottom of the photoresist features.Such a break through may use a recipe like the recipe used for the etchback.

An example of a layer to be etched is may be a conventional etch layer,such as SiN, SiC, an oxide or low-k dielectric. A conventional etchrecipe may be used to etch the layer to be etched.

To strip the photoresist and the sidewall layer (step 120) an oxygenashing may be used.

The forming of the sidewall layer over several cycles provides animproved sidewall layer profile. Providing the sidewall layer throughthe above method has been found to unexpectedly reduce line edgeroughness. In addition, the sidewall layer provides improved selectivitycontrol. It is believed forming a sidewall layer without a top layer orbottom layer can reduce line edge roughness.

In a preferred embodiment of the invention, the deposition of thedeposited layer, etch back, break through etch, and etching of the layerthrough the sidewall layer may be done in situ in the same etch chamber,as shown.

While this invention has been described in terms of several preferredembodiments, there are alterations, permutations, and various substituteequivalents, which fall within the scope of this invention. It shouldalso be noted that there are many alternative ways of implementing themethods and apparatuses of the present invention. It is thereforeintended that the following appended claims be interpreted as includingall such alterations, permutations, and various substitute equivalentsas fall within the true spirit and scope of the present invention.

1-13. (canceled)
 14. A semiconductor device formed by the methodcomprising: forming a photoresist layer over the layer; patterning thephotoresist layer to form photoresist features with photoresistsidewalls; forming a sidewall layer with a thickness less than 100 nmover the sidewalls of the photoresist features, comprising performingfor a plurality of cycles, wherein each cycle comprises depositing alayer on the photoresist layer wherein the deposited layer has athickness between a monolayer to 20 nm; etching features into the layerthrough the photoresist features; and stripping the photoresist layerand sidewall layer. 15-19. (canceled)
 20. A semiconductor device formedby the method, comprising: forming a patterned photoresist layer to overthe etch layer to form photoresist features with photoresist sidewalls;forming a sidewall layer with a thickness less than 100 nm over thesidewalls of the photoresist features, comprising performing for aplurality of cycles, wherein each cycle comprises: depositing a layer onthe photoresist layer wherein the deposited layer has a thicknessbetween a monolayer to 20 nm; and etching back the deposited layer toremove parts of the deposited layer formed over bottoms of thephotoresist features, while leaving a sidewall layer; etching featuresinto the etch layer through the photoresist features; and stripping thephotoresist layer and sidewall layer, wherein the depositing the layeron the photoresist layer, the etching back, the etching features, andstripping are done in situ in a single plasma chamber.
 21. Thesemiconductor device, as recited in claim 14, wherein each cycle of theforming the sidewall layer, further comprises etching back the depositedlayer to remove parts of the deposited layer formed over bottoms of thephotoresist features, while leaving a sidewall layer.
 22. Thesemiconductor device, as recited in claim 21, wherein the depositing thelayer on the photoresist layer, comprises performing at least one ofatomic layer deposition, chemical vapor deposition, sputteringdeposition, plasma deposition, and plasma enhanced chemical vapordeposition, with a bias potential of less than 120 volts.
 23. Thesemiconductor device, as recited in claim 22, further comprising heatingthe substrate to a temperature between −80° C. to 120° C. during thedepositing the layer on the photoresist layer.
 24. The semiconductordevice, as recited in claim 23, wherein the depositing the sidewalllayer over the sidewalls is performed for between 3 and 10 cycles. 25.The semiconductor device, as recited in claim 24, the depositing thelayer on the photoresist layer comprises depositing a layer of at leastone of polymer, TEOS, SiO₂, Si₃N₂, SiC, Si, Al₂O₃, AlN, Cu, HfO₂, Mo,Ta, TaN, TaO₂, Ti, TiN, TiO₂, TiSiN, and W.
 26. The semiconductordevice, as recited in claim 25, further comprising performing a breakthrough etch to etch through any remaining deposited layer.
 27. Thesemiconductor device, as recited in claim 26, wherein the depositing thelayer on the photoresist layer, the etching back, the break through, andthe etching features are done in situ in a single plasma chamber. 28.The semiconductor device, as recited in claim 21, wherein the etchingback further removes parts of the deposited layer over a top of thephotoresist layer.
 29. The semiconductor device, as recited in claim 21,wherein the depositing the layer on the photoresist layer, comprisesperforming at least one of chemical vapor deposition, sputteringdeposition, plasma deposition, and plasma enhanced chemical vapordeposition.
 30. The semiconductor device, as recited in claim 29,wherein the depositing the layer on the photoresist layer furthercomprises providing a bias potential of less than 120 volts.
 31. Thesemiconductor device, as recited in claim 30, wherein the depositing thelayer on the photoresist layer, the etching back, the break through, andthe etching features are done in situ in a single plasma chamber. 32.The semiconductor device, as recited in claim 21, wherein the depositingthe layer on the photoresist layer, the etching back, and the etchingfeatures are done in situ in a single plasma chamber.
 33. Thesemiconductor device, as recited in claim 20, wherein the depositing thelayer on the photoresist layer, comprises performing at least one ofatomic layer deposition, chemical vapor deposition, sputteringdeposition, plasma deposition, and plasma enhanced chemical vapordeposition, with a bias potential of less than 120 volts.
 34. Thesemiconductor device, as recited in claim 33, further comprising heatingthe substrate to a temperature between 80° C. to 120° C. during thedepositing the layer on the photoresist layer.
 35. The semiconductordevice, as recited in claim 20, wherein the depositing the sidewalllayer over the sidewalls is performed for between 3 and 10 cycles. 36.The semiconductor device, as recited in claim 20, wherein the depositingthe layer on the photoresist layer comprises depositing a layer of atleast one of polymer, TEOS, SiO₂, Si₃N₂, SiC, Si, Al₂O₃, AlN, Cu, HfO₂,Mo, Ta, TaN, TaO₂, Ti, TiN, TiO₂, TiSiN, and W.